Modern circuit fabrication typically involves forming of patterns in a layer. Frequently occurring examples include forming a pattern in a dielectric layer for the purpose of defining an electrical interconnection structure, or forming a pattern in a semiconductor layer for the purpose of defining semiconductor structures.
Techniques for patterning a layer include lithography and etching processes (“litho-etch”). A photoresist may be patterned by lithography and the photoresist pattern may thereafter be transferred into an underlying layer by etching. Other patterning techniques include multiple patterning techniques like (litho-etch)x, or pitch splitting techniques such as self-aligned double patterning (SADP) or quadruple patterning (SAQP). Such techniques enable forming of patterns with sub-lithographic critical dimensions.
In many instances, it is desirable to make interrupted or discontinuous line patterns. “Block” or “cut” techniques typically involve forming of a block in a mask pattern, or cutting away a portion of a mask pattern, at a position where an interruption is to be formed. However, certain techniques may be challenging to down-scale to sub-lithographic dimensions. These techniques may also provide limited control over the critical dimensions of the interruption. As pattern densities are ever increasing, this is becoming a growing issue.